SH7211 Datasheet, PDF (41/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 2 CPU
Initial
Bit
Bit Name Value R/W
31 to 15 —
All 0 R
14
BO
0
R/W
13
CS
0
R/W
12 to 10 —
All 0 R
9
M
8
Q
7 to 4
3, 2
I[3:0]
—
—
R/W
—
R/W
1111 R/W
All 0 R
1
S
0
T
—
R/W
—
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
BO Bit
Indicates that a register bank has overflowed.
CS Bit
Indicates that, in CLIP instruction execution, the value
has exceeded the saturation upper-limit value or fallen
below the saturation lower-limit value.
Reserved
These bits are always read as 0. The write value should
always be 0.
M Bit
Q Bit
Used by the DIV0S, DIV0U, and DIV1 instructions.
Interrupt Mask Level
Reserved
These bits are always read as 0. The write value should
always be 0.
S Bit
Specifies a saturation operation for a MAC instruction.
T Bit
True/false condition or carry/borrow bit
(2) Global Base Register (GBR)
GBR is referenced as the base address in a GBR-referencing MOV instruction.
(3) Vector Base Register (VBR)
VBR is referenced as the branch destination base address in the event of an exception or an
interrupt.
(4) Jump Table Base Register (TBR)
TBR is referenced as the start address of a function table located in memory in a
JSR/N@@(disp8,TBR) table-referencing subroutine call instruction.
Rev. 2.00 May. 08, 2008 Page 17 of 1200
REJ09B0344-0200