SH7211 Datasheet, PDF (423/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
• TSR_5
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
- CMFU5 CMFV5 CMFW5
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/(W)*¹ R/(W)*¹R/(W)*¹
Note: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Bit
Bit Name
7 to 3 —
2
CMFU5
Initial
Value
All 0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)*¹ Compare Match/Input Capture Flag U5
Status flag that indicates the occurrence of TGRU_5
input capture or compare match.
[Clearing condition]
• When 0 is written to CMFU5 after reading CMFU5 = 1
[Setting conditions]
• When TCNTU_5 = TGRU_5 and TGRU_5 is
functioning as output compare register
• When TCNTU_5 value is transferred to TGRU_5 by
input capture signal and TGRU_5 is functioning as
input capture register
• When TCNTU_5 value is transferred to TGRU_5 and
TGRU_5 is functioning as a register for measuring the
pulse width of the external input signal. The transfer
timing is specified by the IOC bits in timer I/O control
registers U_5, V_5, and W_5 (TIORU_5, TIORV_5,
and TIORW_5).*²
Rev. 2.00 May. 08, 2008 Page 399 of 1200
REJ09B0344-0200