SH7211 Datasheet, PDF (210/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
8.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 7)
CSnBCR is a 32-bit readable/writable register that specifies the type of memory connected to a
space, data bus width of an area, endian, and the number of waits between access cycles. This
register is initialized to H'36DB0x00 by a power-on reset and retains the value by a manual reset
and in software standby mode.
Do not access external memory other than area 0 until CSnBCR initial setting is completed.
Idle cycles may be inserted even when they are not specified. For details, see section 8.5.10, Wait
between Access Cycles.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
IWW[2:0]
IWRWD[2:0]
IWRWS[2:0]
IWRRD[2:0]
IWRRS[2:0]
Initial value: 0
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
R/W: R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
TYPE[2:0]
ENDIAN BSZ[1:0]
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
1* 1* 0
0
0
0
0
0
0
0
0
R/W: R R/W R/W R/W R/W R/W R/W R
R
R
R
R
R
R
R
R
Note: * CSnBCR samples the external pins (MD1 and MD0) that specify the bus width at power-on reset.
Initial
Bit
Bit Name Value R/W Description
31
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 May. 08, 2008 Page 186 of 1200
REJ09B0344-0200