SH7211 Datasheet, PDF (174/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 7 User Break Controller (UBC)
7.3.4 Break Address Register_1 (BAR_1)
BAR_1 is a 32-bit readable/writable register. BAR_1 specifies the address used as a break
condition in channel 1. The control bits CD1_1 and CD1_0 in the break bus cycle register_1
(BBR_1) select one of the three address buses for a break condition of channel 1. BAR_1 is
initialized to H'00000000 by a power-on reset, but retains its previous value by a manual reset or
in software standby mode or sleep mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BA1_31 BA1_30 BA1_29 BA1_28 BA1_27 BA1_26 BA1_25 BA1_24 BA1_23 BA1_22 BA1_21 BA1_20 BA1_19 BA1_18 BA1_17 BA1_16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BA1_15BA1_14BA1_13BA1_12BA1_11BA1_10 BA1_9 BA1_8 BA1_7 BA1_6 BA1_5 BA1_4 BA1_3 BA1_2 BA1_1 BA1_0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 0 BA1_31 to All 0
BA1_0
R/W Break Address 1
Store an address on the CPU address bus (FAB or
MAB) or IAB specifying break conditions of channel 1.
When the C bus and instruction fetch cycle are
selected by BBR_1, specify an FAB address in bits
BA1_31 to BA1_0.
When the C bus and data access cycle are selected by
BBR_1, specify an MAB address in bits BA1_31 to
BA1_0.
Note: When setting the instruction fetch cycle as a break condition, clear the LSB in BAR_1 to 0.
Rev. 2.00 May. 08, 2008 Page 150 of 1200
REJ09B0344-0200