SH7211 Datasheet, PDF (1016/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 23 Power-Down Modes
Table 23.1 States of Power-Down Modes
State*
Power-Down
Mode
CPU
On-Chip
Transition Conditions CPG CPU Register Memory
On-Chip
Peripheral
Modules
External
Memory
Canceling
Procedure
Sleep mode
Execute SLEEP
Runs
instruction with STBY bit
cleared to 0 in STBCR
Halts
Held
Runs
Runs
(RAM)
Halts
(Flash memory)
Auto-
refreshing
• Interrupt
• Manual reset
• Power-on reset
• DMA address
error
Software
standby mode
Execute SLEEP
Halts
instruction with STBY bit
set to 1 in STBCR
Halts
Held
Halts
(contents are
held)
Halts
Self-
refreshing
• NMI interrupt
• IRQ interrupt
• Manual reset
• Power-on reset
Module standby Set the MSTP bits in
function
STBCR2, STBCR3, and
STBCR4 to 1
Runs
Runs
Held
Specified
module halts
(contents are
held)
Specified
module halts
Auto-
refreshing
• Clear MSTP bit
to 0
• Power-on reset
(only for H-UDI,
UBC, and
DMAC)
Note: * The pin state is retained or set to high impedance. For details, see appendix A, Pin
States.
Rev. 2.00 May. 08, 2008 Page 992 of 1200
REJ09B0344-0200