SH7211 Datasheet, PDF (1181/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
Page
15.3.8 Bit Rate Register 687
(SCBRR)
• Asynchronous mode:
688
Table 15.4 Bit Rates 689
and SCBRR Settings
(Asynchronous Mode)
Table 15.5 Bit Rates 690
and SCBRR Settings
(Clocked Synchronous
Mode)
Table 15.6 Maximum 691
Bit Rates for Various
Frequencies with Baud
Rate Generator
(Asynchronous Mode)
Table 15.7 Maximum
Bit Rates with External
Clock Input
(Asynchronous Mode)
Table 15.8 Maximum
Bit Rates with External
Clock Input
(Clocked Synchronous
Mode, t_Scyc = 12t_pcyc)
15.3.12 Line Status 697
Register (SCLSR)
15.4.2 Operation in 704
Asynchronous Mode
Figure 15.3 Sample
Flowchart for SCIF
Initialization
Revision (See Manual for Details)
Description amended
(1) In normal mode (when the ABCS bit in SCSEMR is 0)
(2) In serial extended mode (when the ABCS bit in SCSEMR
is 1)
Description amended
(1) In normal mode (when the ABCS bit in SCSEMR is 0)
(2) In serial extended mode (when the ABCS bit in SCSEMR
is 1)
Table replaced
Table replaced
Table replaced
Table replaced
Table replaced
Note added
Note: * Only 0 can be written to clear the flag after 1 is read.
Figure amended
Set RTRG[1:0] and TTRG[1:0] in SCFCR,
and clear TFRST and RFRST
Set TE and RE bits in SCSCR to 1,
and set TIE, RIE, and REIE bits
[4]
End of initialization
Rev. 2.00 May. 08, 2008 Page 1157 of 1200
REJ09B0344-0200