SH7211 Datasheet, PDF (575/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.7.3 Caution on Period Setting
When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
• Channel 0 to 4
Pφ
f=
(N + 1)
• Channel 5
Pφ
f=
N
Where f:
Counter frequency
Pφ: Peripheral clock operating frequency
N: TGR set value
10.7.4 Contention between TCNT Write and Clear Operations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes
precedence and the TCNT write is not performed.
Figure 10.119 shows the timing in this case.
TCNT write cycle
T1 T2
Pφ
Address
TCNT address
Write signal
Counter clear
signal
TCNT
N
H'0000
Figure 10.119 Contention between TCNT Write and Clear Operations
Rev. 2.00 May. 08, 2008 Page 551 of 1200
REJ09B0344-0200