SH7211 Datasheet, PDF (265/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
CK
A25 to A0
CS5
RD/WR
AH
Read
RD
D15/D7 to D0
Write
WEn
D15/D7 to D0
BS
DACKn*
Ta1
Tadw
Ta2
Ta3
Address
Address
T1
T2
Data
Data
Note: * The waveform for DACKn is when active low is specified.
Figure 8.11 Access Timing for MPX Space (Address Cycle Wait 1, Data Cycle No Wait)
Rev. 2.00 May. 08, 2008 Page 241 of 1200
REJ09B0344-0200