SH7211 Datasheet, PDF (94/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 4 Clock Pulse Generator (CPG)
Bit
6 to 4
3
2 to 0
Bit Name
IFC[2:0]
Initial
Value
000
RNGS
0
PFC[2:0] 011
R/W Description
R/W Internal Clock (Iφ) Frequency Division Ratio
These bits specify the frequency division ratio of the
internal clock with respect to the output frequency of
PLL circuit 1.
If a prohibited value is specified, correct operation
cannot be guaranteed.
000: × 1 time
001: × 1/2 time
011: × 1/4 time
Other than above: Setting prohibited
R/W Set this bit according to the output frequency of PLL
circuit 1.
0: High-frequency mode
1: Low-frequency mode
Always specify high-frequency mode for this LSI.
Do not set this bit to 1.
R/W Peripheral Clock (Pφ) Frequency Division Ratio
These bits specify the frequency division ratio of the
peripheral clock with respect to the output frequency
of PLL circuit 1.
If a prohibited value is specified, correct operation
cannot be guaranteed.
000: × 1 time
001: × 1/2 time
011: × 1/4 time
101: × 1/8 time
Other than above: Setting prohibited
Rev. 2.00 May. 08, 2008 Page 70 of 1200
REJ09B0344-0200