SH7211 Datasheet, PDF (721/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 15 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
15 to 1 —
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
ORER
0
R/(W)* Overrun Error
Indicates the occurrence of an overrun error.
0: Receiving is in progress or has ended normally*¹
[Clearing conditions]
• ORER is cleared to 0 when the chip is a power-on
reset
• ORER is cleared to 0 when 0 is written after 1 is
read from ORER.
1: An overrun error has occurred*²
[Setting condition]
• ORER is set to 1 when the next serial receiving is
finished while the receive FIFO is full of 16-byte
receive data.
Notes: 1. Clearing the RE bit to 0 in SCSCR does
not affect the ORER bit, which retains its
previous value.
2. The receive FIFO data register (SCFRDR)
retains the data before an overrun error
has occurred, and the next received data
is discarded. When the ORER bit is set to
1, the SCIF cannot continue the next
serial reception.
Note: * Only 0 can be written to clear the flag after 1 is read.
Rev. 2.00 May. 08, 2008 Page 697 of 1200
REJ09B0344-0200