SH7211 Datasheet, PDF (268/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
This LSI
A14
A1
CKE
CK
CSn
64M SDRAM
(1M × 16-bit × 4-bank)
A13
A0
CKE
CLK
CS
RASL
CASL
RD/WR
D15
D0
DQMLU
DQMLL
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
Figure 8.13 Example of 16-Bit Data Width SDRAM Connection
(RASU and CASU are Not Used)
(2) Address Multiplexing
An address multiplexing is specified so that SDRAM can be connected without external
multiplexing circuitry according to the setting of bits BSZ[1:0] in CSnBCR, bits A2ROW[1:0],
and A2COL[1:0], A3ROW[1:0], and A3COL[1:0] in SDCR. Tables 8.9 to 8.11 show the
relationship between the settings of bits BSZ[1:0], A2ROW[1:0], A2COL[1:0], A3ROW[1:0], and
A3COL[1:0] and the bits output at the address pins. Do not specify those bits in the manner other
than this table, otherwise the operation of this LSI is not guaranteed. A29 to A18 are not
multiplexed and the original values of address are always output at these pins.
The A0 pin of SDRAM specifies a word address. Therefore, connect the A0 pin of SDRAM to the
A1 pin of the LSI; then connect the A1 pin of SDRAM to the A2 pin of the LSI, and so on.
Rev. 2.00 May. 08, 2008 Page 244 of 1200
REJ09B0344-0200