SH7211 Datasheet, PDF (226/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
• CS5WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
SZSEL
MPXW/
BAS
-
WW[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
SW[1:0]
WR[3:0]
WM
-
-
-
-
HW[1:0]
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W
Bit
31 to 22
Bit Name
⎯
Initial
Value
All 0
21
SZSEL
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W MPX-I/O Interface Bus Width Specification
Specifies an address to select the bus width when the
BSZ[1:0] of CS5BCR are specified as 11. This bit is
valid only when area 5 is specified as MPX-I/O.
0: Selects the bus width by address A14
1: Selects the bus width by address A21
The relationship between the SZSEL bit and bus width
selected by A14 or A21 are summarized below.
SZSEL A14
A21
Bus Width
0
0
Not affected 8 bits
0
1
Not affected 16 bits
1
Not affected 0
8 bits
1
Not affected 1
16 bits
Rev. 2.00 May. 08, 2008 Page 202 of 1200
REJ09B0344-0200