SH7211 Datasheet, PDF (550/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
(2) MTU2S Counter Clearing Caused by MTU2 Flag Setting Source (MTU2–MTU2S
Synchronous Counter Clearing)
The MTU2S counters can be cleared by sources for setting the flags in TSR_0 to TSR_2 in the
MTU2 through the TSYCR_3 settings in the MTU2S.
(a) Example of Procedure for Specifying MTU2S Counter Clearing by MTU2 Flag Setting
Source
Figure 10.85 shows an example of procedure for specifying MTU2S counter clearing by MTU2
flag setting source.
MTU2S counter clearing by
MTU2S flag setting source
Stop count operation
Set TSYCR_3
Start channel 3 or 4 in MTU2S
[1] Use TSTR registers in the MTU2 and MTU2S and halt the
counters used for this function.
[2] Use TSYCR_3 in the MTU2S to specify the flag setting source
to be used for the TCNT_3 and TCNT_4 clearing source.
[1]
[3] Start TCNT_3 or TCNT_4 in the MTU2S.
[2] [4] Start TCNT_0, TCNT_1, or TCNT_2 in the MTU2.
Note: The TSYCR_3 setting is ignored while the counter is
stopped. The setting becomes valid after TCNT_3 or
[3]
TCNT4 is started.
Start one of channels 0 to 2 in MTU2 [4]
<Counter clearing by flag setting>
Figure 10.85 Example of Procedure for Specifying MTU2S Counter
Clearing by MTU2 Flag Setting Source
Rev. 2.00 May. 08, 2008 Page 526 of 1200
REJ09B0344-0200