SH7211 Datasheet, PDF (218/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
• CS1WCR, CS7WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
BAS
-
WW[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R R/W R R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
SW[1:0]
WR[3:0]
WM
-
-
-
-
HW[1:0]
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W
Bit
Bit Name
31 to 21 ⎯
Initial
Value
All 0
20
BAS
0
19
⎯
0
18 to 16 WW[2:0] 000
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SRAM with Byte Selection Byte Access Select
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read/write timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn signal during the read/write access
cycle and asserts the RD/WR signal at the write
timing.
Reserved
This bit is always read as 0. The write value should
always be 0.
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
000: The same cycles as WR[3:0] setting (number of
read access wait cycles)
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
Rev. 2.00 May. 08, 2008 Page 194 of 1200
REJ09B0344-0200