SH7211 Datasheet, PDF (247/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
Bit
10
9
8
7 to 5
Bit Name
RMODE
PDOWN
BACTV
⎯
Initial
Value
0
0
0
All 0
R/W Description
R/W Refresh Control
Specifies whether to perform auto-refresh or self-
refresh when the RFSH bit is 1. When the RFSH bit is
1 and this bit is 1, self-refresh starts immediately.
When the RFSH bit is 1 and this bit is 0, auto-refresh
starts according to the contents that are set in registers
RTCSR, RTCNT, and RTCOR.
0: Auto-refresh is performed
1: Self-refresh is performed
R
Power-Down Mode
Specifies whether the SDRAM will enter power-down
mode after the access to the SDRAM. With this bit
being set to 1, after the SDRAM is accessed, the CKE
signal is driven low and the SDRAM enters power-
down mode.
0: The SDRAM does not enter power-down mode after
being accessed.
1: The SDRAM enters power-down mode after being
accessed.
R/W Bank Active Mode
Specifies to access whether in auto-precharge mode
(using READA and WRITA commands) or in bank
active mode (using READ and WRIT commands).
0: Auto-precharge mode (using READA and WRITA
commands)
1: Bank active mode (using READ and WRIT
commands)
Note:
Bank active mode can be set only in area 3,
and only the 16-bit bus width can be set. When
both the CS2 and CS3 spaces are set to
SDRAM, specify auto-precharge mode.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 May. 08, 2008 Page 223 of 1200
REJ09B0344-0200