SH7211 Datasheet, PDF (327/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 9 Direct Memory Access Controller (DMAC)
9.3 Register Descriptions
The DMAC has the registers listed in table 9.2. There are four control registers and three reload
registers for each channel, and one common control register is used by all channels. In addition,
there is one extension resource selector per two channels. Each channel number is expressed in the
register names, as in SAR_0 for SAR in channel 0.
Table 9.2 Register Configuration
Channel
0
1
Register Name
Abbreviation R/W Initial Value
DMA source address SAR_0
register_0
R/W H'00000000
DMA destination
address register_0
DAR_0
R/W H'00000000
DMA transfer count
register_0
DMATCR_0 R/W H'00000000
DMA channel control CHCR_0
register_0
R/W*¹ H'00000000
DMA reload source
address register_0
RSAR_0
R/W H'00000000
DMA reload destination RDAR_0
address register_0
R/W H'00000000
DMA reload transfer RDMATCR_0 R/W H'00000000
count register_0
DMA source address SAR_1
register_1
R/W H'00000000
DMA destination
address register_1
DAR_1
R/W H'00000000
DMA transfer count
register_1
DMA channel control
register_1
DMATCR_1 R/W H'00000000
CHCR_1
R/W*¹ H'00000000
DMA reload source
address register_1
RSAR_1
R/W H'00000000
DMA reload destination RDAR_1
address register_1
R/W H'00000000
DMA reload transfer RDMATCR_1 R/W H'00000000
count register_1
Address
Access
Size
H'FFFE1000 16, 32
H'FFFE1004 16, 32
H'FFFE1008 16, 32
H'FFFE100C 8, 16, 32
H'FFFE1100 16, 32
H'FFFE1104 16, 32
H'FFFE1108 16, 32
H'FFFE1010 16, 32
H'FFFE1014 16, 32
H'FFFE1018 16, 32
H'FFFE101C 8, 16, 32
H'FFFE1110 16, 32
H'FFFE1114 16, 32
H'FFFE1118 16, 32
Rev. 2.00 May. 08, 2008 Page 303 of 1200
REJ09B0344-0200