SH7211 Datasheet, PDF (835/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 19 Pin Function Controller (PFC)
19.1.1 Port A I/O Registers H, L (PAIORH, PAIORL)
PAIORH and PAIORL are 16-bit readable/writable registers that are used to set the pins on port A
as inputs or outputs. Bits PA25IOR to PA0IOR correspond to pins PA25 to PA0. PAIORH and
PAIORL are enabled when the port A pins are functioning as general-purpose inputs/outputs
(PA25 to PA0) and for the TIOC input/output of the MTU2. In other states, they are disabled. A
given pin on port A will be an output pin if the corresponding bit in PAIORH or PAIORL is set to
1, and an input pin if the bit is cleared to 0.
Bits 15 to 10 of PAIORH are reserved. These bits are always read as 0. The write value should
always be 0.
PAIORH and PAIORL are initialized to H'0000 by a power-on reset; but are not initialized by a
manual reset or in sleep mode or software standby mode.
(1) Port A I/O Register H (PAIORH)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
PA25 PA24 PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16
IOR IOR IOR IOR IOR IOR IOR IOR IOR IOR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
(2) Port A I/O Register L (PAIORL)
Bit:
Initial value:
R/W:
15
PA15
IOR
0
R/W
14
PA14
IOR
0
R/W
13
PA13
IOR
0
R/W
12
PA12
IOR
0
R/W
11
PA11
IOR
0
R/W
10
PA10
IOR
0
R/W
9
PA9
IOR
0
R/W
8
PA8
IOR
0
R/W
7
PA7
IOR
0
R/W
6
PA6
IOR
0
R/W
5
PA5
IOR
0
R/W
4
PA4
IOR
0
R/W
3
PA3
IOR
0
R/W
2
PA2
IOR
0
R/W
1
PA1
IOR
0
R/W
0
PA0
IOR
0
R/W
Rev. 2.00 May. 08, 2008 Page 811 of 1200
REJ09B0344-0200