SH7211 Datasheet, PDF (306/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
CK
A25 to A0
CSn
WEn
T1
T2
RD/WR
Read
RD
D15 to D0
Write
RD/WR
RD
High
D15 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 8.34 Basic Access Timing for SRAM with Byte Selection (BAS = 1)
Rev. 2.00 May. 08, 2008 Page 282 of 1200
REJ09B0344-0200