SH7211 Datasheet, PDF (938/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 21 Flash Memory
(3.3) Flash Pass/Fail Result Parameter (FPFR: General Register R0 of CPU)
This parameter indicates the return value of the program processing result.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
-
Initial value: -
R/W: R/W
14
-
-
R/W
13
-
-
R/W
12
-
-
R/W
11
-
-
R/W
10
-
-
R/W
9
-
-
R/W
8
-
-
R/W
7
-
-
R/W
6
MD
-
R/W
5
EE
-
R/W
4
FK
-
R/W
3
-
-
R/W
2
WD
-
R/W
1
WA
-
R/W
0
SF
-
R/W
Initial
Bit
Bit Name Value
R/W
31 to 7 ⎯
Undefined R/W
6
MD
Undefined R/W
Description
Unused
Return 0.
Programming Mode Related Setting Error Detect
Returns the check result of whether the signal input to
the FWE pin is high and whether the error protection
state is not entered.
When a low-level signal is input to the FWE pin or the
error protection state is entered, 1 is written to this bit.
The input level to the FWE pin and the error protection
state can be confirmed with the FWE bit (bit 7) and the
FLER bit (bit 4) in FCCS, respectively. For conditions to
enter the error protection state, see section 21.6.3,
Error Protection.
0: FWE and FLER settings are normal (FWE = 1, FLER
= 0)
1: FWE = 0 or FLER = 1, and programming cannot be
performed
Rev. 2.00 May. 08, 2008 Page 914 of 1200
REJ09B0344-0200