SH7211 Datasheet, PDF (581/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.7.10 Contention between TGR Write and Input Capture
If an input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed for channels 0 to 4. For channel
5, write to TGR is performed and the input capture signal is generated.
Figures 10.126 and 127 show the timing in this case.
Pφ
Address
Write signal
Input capture
signal
TCNT
TGR write cycle
T1 T2
TGR address
M
TGR
M
Figure 10.126 Contention between TGR Write and Input Capture (Channels 0 to 4)
Pφ
Address
Write signal
Input capture
signal
TCNT
TGR
TGR write cycle
T1 T2
TGR address
M
TGR write data
N
Figure 10.127 Contention between TGR Write and Input Capture (Channel 5)
Rev. 2.00 May. 08, 2008 Page 557 of 1200
REJ09B0344-0200