SH7211 Datasheet, PDF (261/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 8.8. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled on the falling edge of CK at the transition from the T1 or Tw
cycle to the T2 cycle.
Wait states inserted
by WAIT signal
T1
Tw
Tw
Twx
T2
Read
Write
CK
A25 to A0
CSn
RD/WR
RD
D15 to D0
WEn
D15 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 8.8 Wait Cycle Timing for Normal Space Access
(Wait Cycle Insertion Using WAIT Signal)
Rev. 2.00 May. 08, 2008 Page 237 of 1200
REJ09B0344-0200