SH7211 Datasheet, PDF (215/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
8.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 7)
CSnWCR specifies various wait cycles for memory access. The bit configuration of this register
varies as shown below according to the memory type (TYPE2 to TYPE0) specified by the CSn
space bus control register (CSnBCR). Specify CSnWCR before accessing the target area. Specify
CSnBCR first, then specify CSnWCR.
CSnWCR is initialized to H'00000500 by a power-on reset and retains the value by a manual reset
and in software standby mode.
(1) Normal Space, SRAM with Byte Selection, MPX-I/O
• CS0WCR
Bit:
Initial value:
R/W:
31
-
0
R/W
30
-
0
R/W
29
-
0
R/W
28
-
0
R/W
27
-
0
R/W
26
-
0
R/W
25
-
0
R/W
24
-
0
R/W
23
-
0
R/W
22
-
0
R/W
21
-
0
R/W
20
BAS
0
R/W
19
-
0
R/W
18
-
0
R/W
17
-
0
R/W
16
-
0
R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
SW[1:0]
WR[3:0]
WM
-
-
-
-
HW[1:0]
Initial value: 0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
R
R R/W R/W
Bit
Bit Name
31 to 21 ⎯ *
20
BAS*
Initial
Value
All 0
0
R/W Description
R/W Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Byte Access Selection when SRAM with Byte
Selection is Used
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read/write timing and
asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn signal during the read/write access
cycle and asserts the RD/WR signal at the write
timing.
Rev. 2.00 May. 08, 2008 Page 191 of 1200
REJ09B0344-0200