SH7211 Datasheet, PDF (195/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 7 User Break Controller (UBC)
(Example 1-3)
• Register specifications
BBR_0 = H'0054, BAR_0 = H'00008404, BAMR_0 = H'00000FFF, BBR_1 = H'0054,
BAR_1 = H'00008010, BAMR_1 = H'00000006, BRCR = H'00000020
<Channel 0>
Address: H'00008404, Address mask: H'00000FFF
Bus cycle: C bus/instruction fetch (after instruction execution)/read (operand size is not
included in the condition)
<Channel 1>
Address: H'00008010, Address mask: H'00000006
Bus cycle: C bus/instruction fetch (before instruction execution)/read (operand size is not
included in the condition)
A user break occurs after an instruction with addresses H'00008000 to H'00008FFE is executed
or before an instruction with addresses H'00008010 to H'00008016 are executed.
(2) Break Condition Specified for C Bus Data Access Cycle
(Example 2-1)
• Register specifications
BBR_0 = H'0064, BAR_0 = H'00123456, BAMR_0 = H'00000000,
BBR_1 = H'006A, BAR_1 = H'000ABCDE, BAMR_1 = H'000000FF, BRCR = H'00000000
<Channel 0>
Address: H'00123456, Address mask: H'00000000
Bus cycle: C bus/data access/read (operand size is not included in the condition)
<Channel 1>
Address: H'000ABCDE, Address mask: H'000000FF
Bus cycle: C bus/data access/write/word
On channel 0, a user break occurs with longword read from address H'00123456, word read
from address H'00123456, or byte read from address H'00123456. On channel 1, a user break
occurs when word is written in addresses H'000ABC00 to H'000ABCFE.
Rev. 2.00 May. 08, 2008 Page 171 of 1200
REJ09B0344-0200