SH7211 Datasheet, PDF (1117/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 27 Electrical Characteristics
27.4.2 Control Signal Timing
Table 27.7 Control Signal Timing
Conditions: Vcc = PLLVcc = 1.4 to 1.6 V, VccQ = 3.0 to 3.6,
Vss = PLLVss = VssQ = 0 V, Ta = −40°C to +85°C
Bφ = 40 MHz
Item
Symbol Min.
Max.
Unit Figure
RES pulse width
RES setup time *¹
RES hold time
t_RESW
20*²
–
t_RESS
25
–
t
15
–
RESH
t_cyc
Figure 27.5,
ns ^{Figure 27.6,}
Figure 27.8,
ns _{Figure 27.9}
MRES pulse width
t_MRESW
20*³
—
t_cyc
MRES setup time
t_MRESS
25
–
ns
MRES hold time
t_MRESH
15
–
ns
MD1, MD0 setup time
t_MDS
20
–
t_cyc
Figure 27.8
BREQ setup time
t_BREQS
1/2t_cyc + 10 –
ns Figure 27.10
BREQ hold time
t_BREQH
1/2t_cyc + 4 –
ns
NMI setup time *¹
t_NMIS
15
–
ns Figure 27.9
NMI hold time
t_NMIH
7
–
ns
IRQ7 to IRQ0 setup time *¹
t_IRQS
15
–
ns
IRQ7 to IRQ0 hold time
t_IRQH
7
–
ns
IRQOUT/REFOUT output delay time t_IRQOD
—
100
ns Figure 27.11
BACK delay time
t_BACKD
—
1/2t_cyc + 20 ns Figure 27.10
Bus tri-state delay time 1
t_BOFF1
0
100
ns
Bus tri-state delay time 2
t_BOFF2
0
100
ns
Bus buffer on time 1
t_BON1
0
30
ns
Bus buffer on time 2
t_BON2
0
30
ns
Notes: 1. RES, NMI, and IRQ7 to IRQ0 are asynchronous signals. When these setup times are
observed, a change of these signals is detected at the clock rising edge. If the setup
times are not observed, detection of a signal change may be delayed until the next
rising edge of the clock.
2. In standby mode or when the clock multiplication ratio is changed, t = t (Min. 10
RESW
OSC2
ms).
3. In standby mode, t_RESW = t_OSC2 (Min. 10 ms).
Rev. 2.00 May. 08, 2008 Page 1093 of 1200
REJ09B0344-0200