SH7211 Datasheet, PDF (1103/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 26 List of Registers
Module
Name
Register
Power-On Manual
Abbreviation Reset
Reset
Software
Standby
Module
Standby
Sleep
I/O port
PADRH
Initialized Retained Retained ⎯
Retained
PADRL
Initialized Retained Retained ⎯
Retained
PAPRH
Undefined Retained Retained ⎯
Retained
PAPRL
Undefined Retained Retained ⎯
Retained
PBDRH
Initialized Retained Retained ⎯
Retained
PBDRL
Initialized Retained Retained ⎯
Retained
PBPRH
Undefined Retained Retained ⎯
Retained
PBPRL
Undefined Retained Retained ⎯
Retained
PDDRL
Initialized Retained Retained ⎯
Retained
PDPRL
Undefined Retained Retained ⎯
Retained
PFDR
Initialized Retained Retained ⎯
Retained
FLASH
FCCS
Initialized Retained Initialized Initialized Retained
FPCS
Initialized Retained Initialized Initialized Retained
FECS
Initialized Retained Initialized Initialized Retained
FKEY
Initialized Retained Initialized Initialized Retained
FMATS
Initialized Retained Initialized Initialized Retained
FTDAR
Initialized Retained Initialized Initialized Retained
Power-
down
mode
STBCR
STBCR2
SYSCR1
Initialized Retained Retained ⎯
Initialized Retained Retained ⎯
Initialized Retained Retained ⎯
Retained
Retained
Retained
SYSCR2
Initialized Retained Retained ⎯
Retained
STBCR3
Initialized Retained Retained ⎯
Retained
STBCR4
Initialized Retained Retained ⎯
Retained
H-UDI*³
SDIR
Retained Retained Retained Retained Retained
Notes: 1. Retains the previous value after an internal power-on reset by means of the WDT.
2. Bits BN[3:0] are initialized.
3. Initialized by TRST assertion or in the Test-Logic-Reset state of the TAP controller.
Rev. 2.00 May. 08, 2008 Page 1079 of 1200
REJ09B0344-0200