SH7211 Datasheet, PDF (1154/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 27 Electrical Characteristics
27.4.9 SCIF Module Timing
Table 27.14 SCIF Module Timing
Conditions: Vcc = PLLVcc = 1.4 V to 1.6 V, VccQ = 3.0 V to 3.6 V,
Vss = PLLVss = VssQ = 0 V, Ta = −40°C to +85°C
Item
Symbol Min.
Input clock cycle (clocked synchronous) t_Scyc
12
(asynchronous)
4
Input clock rise time
Input clock fall time
Input clock width
Transmit data delay time
(clocked synchronous)
t_SCKr
—
t_SCKf
—
t_SCKW
0.4
t_TXD
—
Receive data setup time
(clocked synchronous)
t
100
RXS
Receive data hold time
(clocked synchronous)
t_RXH
100
Note: t indicates peripheral clock (Pφ) cycle.
pcyc
Max.
—
—
1.5
1.5
0.6
100
—
—
Unit
t_pcyc
t_pcyc
t_pcyc
t_pcyc
t_Scyc
t_pcyc
Figure
Figure 27.46
Figure 27.46
Figure 27.46
Figure 27.46
Figure 27.46
Figure 27.47
ns Figure 27.47
ns Figure 27.47
SCK
t_SCKW
t_SCKr
t_Scyc
t_SCKf
Figure 27.46 SCK Input Clock Timing
SCK
(input/output)
TXD
(data transmit)
RXD
(data receive)
t_Scyc
t_TXD
t_RXS t_RXH
Figure 27.47 SCIF Input/Output Timing in Clocked Synchronous Mode
Rev. 2.00 May. 08, 2008 Page 1130 of 1200
REJ09B0344-0200