SH7211 Datasheet, PDF (101/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 5 Exception Handling
Section 5 Exception Handling
5.1 Overview
5.1.1 Types of Exception Handling and Priority
Exception handling is started by sources, such as resets, address errors, register bank errors,
interrupts, and instructions. Table 5.1 shows their priorities. When several exception handling
sources occur at once, they are processed according to the priority shown.
Table 5.1 Types of Exception Handling and Priority Order
Type
Reset
Address
error
Instruction
Register
bank error
Interrupt
Exception Handling
Power-on reset
Manual reset
CPU address error
DMAC address error
Integer division exception (division by zero)
Integer division exception (overflow)
Bank underflow
Bank overflow
NMI
User break
H-UDI
IRQ
On-chip peripheral modules A/D converter (ADC)
Direct memory access controller (DMAC)
Compare match timer (CMT)
Bus state controller (BSC)
Watchdog timer (WDT)
Multi-function timer pulse unit 2 (MTU2)
Port output enable 2 (POE2): OEI1 and
OEI2 interrupts
Priority
High
Low
Rev. 2.00 May. 08, 2008 Page 77 of 1200
REJ09B0344-0200