SH7211 Datasheet, PDF (957/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 21 Flash Memory
The frequency division ratio of an internal clock (Iφ), a bus clock (Bφ), and a peripheral clock (Pφ)
is specified as 4:4:4 by the frequency control register (FRQCR).
For the downloaded on-chip program area, see the RAM map for programming/erasing in figure
21.10.
A single divided block is erased by one erasing processing. For block divisions, see figure 21.4.
To erase two or more blocks, update the erase block number and perform the erasing processing
for each block.
(3.1) Select the on-chip program to be downloaded and the download destination address
Set the EPVB bit in FECS to 1.
Several programming/erasing programs cannot be selected at one time. If several programs are
set, download is not performed and a download error is returned to the source select error
detect (SS) bit in the DPFR parameter.
Specify the start address of the download destination by FTDAR.
The procedures to be carried out after setting FKEY, e.g. download and initialization, are the
same as those in the programming procedure. For details, see the description in section 21.5.2
(2), Programming Procedure in User Program Mode.
(3.2) Set the FEBS parameter necessary for erasure
Set the erase block number of the user MAT in the flash erase block select parameter (FEBS:
general register R4). If a value other than an erase block number of the user MAT is set, no
block is erased even though the erasing program is executed, and an error is returned to the
return value parameter FPFR.
(3.3) Erasure
Similar to as in programming, there is an entry point of the erasing program in the area from
(download start address set by FTDAR) + 16 bytes of on-chip RAM. The subroutine is called
and erasing is executed by using the following steps.
MOV.L #DLTOP+16,R1
JSR @R1
NOP
; Set entry address to R1
; Call erasing routine
1. The general registers other than R0 are saved in the erasing program.
2. R0 is a return value of the FPFR parameter.
3. Since the stack area is used in the erasing program, a stack area of maximum 128 bytes
must be reserved in RAM.
Rev. 2.00 May. 08, 2008 Page 933 of 1200
REJ09B0344-0200