SH7211 Datasheet, PDF (663/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 13 Compare Match Timer (CMT)
13.2.1 Compare Match Timer Start Register (CMSTR)
CMSTR is a 16-bit register that selects whether compare match counter (CMCNT) operates or is
stopped.
CMSTR is initialized to H'0000 by a power-on reset or in software standby mode, but retains its
previous value in module standby mode.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
- STR1 STR0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W
Bit
Bit Name
15 to 2 ⎯
1
STR1
0
STR0
Initial
Value
All 0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Count Start 1
Specifies whether compare match counter_1 operates
or is stopped.
0: CMCNT_1 count is stopped
1: CMCNT_1 count is started
R/W Count Start 0
Specifies whether compare match counter_0 operates
or is stopped.
0: CMCNT_0 count is stopped
1: CMCNT_0 count is started
Rev. 2.00 May. 08, 2008 Page 639 of 1200
REJ09B0344-0200