SH7211 Datasheet, PDF (202/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 8 Bus State Controller (BSC)
8.2 Input/Output Pins
Table 8.1 shows the pin configuration of the BSC.
Table 8.1 Pin Configuration
Name
A25 to A0
D15 to D0
BS
CS0 to CS7
RD/WR
I/O
Output
I/O
Output
Output
Output
RD
Output
AH
Output
WE1/DQMLU Output
WE0/DQMLL Output
RASL
CASL
CKE
WAIT
BREQ
BACK
REFOUT
MD1, MD0
Output
Output
Output
Input
Input
Output
Output
Input
Function
Address bus
Data bus
Bus cycle start
Chip select
Read/write
Connects to WE pins when SDRAM or SRAM with byte selection is
connected.
Read pulse signal (read data output enable signal)
Functions as a strobe signal for indicating memory read cycles when
PCMCIA is used.
A signal used to hold an address when MPX-I/O is in use
Indicates that D15 to D8 are being written to.
Connected to the byte select signal when a SRAM with byte selection is
connected.
Functions as the select signals for D15 to D8 when SDRAM is
connected.
Indicates that D7 to D0 are being written to.
Connected to the byte select signal when a SRAM with byte selection is
connected.
Functions as the select signals for D7 to D0 when SDRAM is connected.
Connects to RAS pin when SDRAM is connected.
Connects to CAS pin when SDRAM is connected.
Connects to CKE pin when SDRAM is connected.
External wait input
Bus request input
Bus enable output
Refresh request output in bus-released state
Select bus width (8 or 16 bits) of area 0 and modes including
enabling/disabling of the on-chip ROM.
Rev. 2.00 May. 08, 2008 Page 178 of 1200
REJ09B0344-0200