SH7211 Datasheet, PDF (129/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 6 Interrupt Controller (INTC)
6.3.1 Interrupt Priority Registers 01, 02, 05 to 15 (IPR01, IPR02, IPR05 to IPR15)
IPR01, IPR02, and IPR05 to IPR15 are 16-bit readable/writable registers in which priority levels
from 0 to 15 are set for IRQ interrupts, PINT interrupts, and on-chip peripheral module interrupts.
Table 6.3 shows the correspondence between the interrupt request sources and the bits in IPR01,
IPR02, and IPR05 to IPR15.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Table 6.3 Interrupt Request Sources and IPR01, IPR02, and IPR05 to IPR15
Register Name
Interrupt priority
register 01
Interrupt priority
register 02
Interrupt priority
register 05
Interrupt priority
register 06
Interrupt priority
register 07
Interrupt priority
register 08
Interrupt priority
register 09
Interrupt priority
register 10
Interrupt priority
register 11
Interrupt priority
register 12
Bits 15 to 12
IRQ0
IRQ4
Reserved
DMAC0
DMAC4
CMT0
MTU0
(TGI0A to TGI0D)
MTU2
(TGI2A, TGI2B)
MTU4
(TGI4A to TGI4D)
MTU3S
(TGI3A to TGI3D)
Bits 11 to 8
IRQ1
Bits 7 to 4
IRQ2
Bits 3 to 0
IRQ3
IRQ5
IRQ6
IRQ7
Reserved
ADI
Reserved
DMAC1
DMAC2
DMAC3
DMAC5
DMAC6
DMAC7
CMT1
BSC
WDT
MTU0
(TCI0V, TGI0E,
TGI0F)
MTU2
(TCI2V, TCI2U)
MTU4
(TCI4V)
MTU3S
(TCI3V)
MTU1
MTU1
(TGI1A, TGI1B) (TCI1V, TCI1U)
MTU3
MTU3
(TGI3A to TGI3D) (TCI3V)
MTU5
(TGI5U, TGI5V,
TGI5W)
POE2
(OEI1, OEI2)
MTU4S
MTU4S
(TGI4A to TGI4D) (TCI4V)
Rev. 2.00 May. 08, 2008 Page 105 of 1200
REJ09B0344-0200