SH7211 Datasheet, PDF (579/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.7.8 Contention between Buffer Register Write and TCNT Clear
When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register
(TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to
TGR by the buffer operation is the data before write.
Figure 10.123 shows the timing in this case.
Pφ
Address
Write signal
TCNT clear
signal
Buffer transfer
signal
Buffer register
TGR write cycle
T1
T2
Buffer register
address
Buffer register write data
N
M
TGR
N
Figure 10.123 Contention between Buffer Register Write and TCNT Clear
Rev. 2.00 May. 08, 2008 Page 555 of 1200
REJ09B0344-0200