SH7211 Datasheet, PDF (812/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 17 A/D Converter (ADC)
17.4.5 External Trigger Input Timing
The A/D conversion can be externally triggered. To input an external trigger, set the pin function
controller (PFC) to select ADTRG pin function and drive the ADTRG pin low when a high level
is input to the ADTRG pin with the TRGE and EXTRG bits in ADCR are both set to 1. A falling
edge of the ADTRG pin sets the ADST bit in ADCR to 1, starting the A/D conversion. Other
operations are conducted in the same way for all A/D conversion activation sources. Figure 17.5
shows the timing.
The ADST bit is set to 1 after 5 states has elapsed from the point at which the A/D converter
detects a falling edge on the ADTRG pin. A low level input to the ADTRG pin must be made after
the ADCR, ADSTRGR, and ADANSR registers have been set.
Pφ
ADTRG
External trigger
signal
ADST
A/D conversion
Figure 17.5 External Trigger Input Timing
17.4.6 Example of ADDR Auto-Clear Function
When the A/D data register (ADDR) is read by the CPU or DMAC, ADDR can be automatically
cleared to H'0000 by setting the ACE bit in ADCR to 1. This function allows the detection of non-
updated ADDR states.
Figure 17.6 shows an example of when the auto-clear function of ADDR is disabled (normal state)
and enabled.
Rev. 2.00 May. 08, 2008 Page 788 of 1200
REJ09B0344-0200