SH7211 Datasheet, PDF (932/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 21 Flash Memory
(2) Programming/Erasing Initialization
The on-chip programming/erasing program to be downloaded includes the initialization program.
The specified period pulse must be applied when programming or erasing. The specified pulse
width is made by the method in which wait loop is configured by the CPU instruction. The
operating frequency of the CPU must be set. Since the user branch function is supported, the user
branch destination address must be set.
The initial program is set as a parameter of the programming/erasing program which has
downloaded these settings.
(2.1) Flash Programming/Erasing Frequency Parameter (FPEFEQ: General Register R4 of
CPU)
This parameter sets the operating frequency of the CPU.
The flash programming/erasing frequency Iφ of this LSI is limited to 32 to 40 MHz.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
F15
Initial value: -
R/W: R/W
14
F14
-
R/W
13
F13
-
R/W
12
F12
-
R/W
11
F11
-
R/W
10
F10
-
R/W
9
F9
-
R/W
8
F8
-
R/W
7
F7
-
R/W
6
F6
-
R/W
5
F5
-
R/W
4
F4
-
R/W
3
F3
-
R/W
2
F2
-
R/W
1
F1
-
R/W
0
F0
-
R/W
Rev. 2.00 May. 08, 2008 Page 908 of 1200
REJ09B0344-0200