SH7211 Datasheet, PDF (1023/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 23 Power-Down Modes
23.3.4 Standby Control Register 4 (STBCR4)
STBCR4 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. STBCR4 is initialized to H'F4 by a power-on reset but retains its previous value by a
manual reset or in software standby mode. Only byte access is possible.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP
47
46
45
44
-
MSTP MSTP
42
41
-
Initial value: 1
1
1
1
0
1
1
0
R/W: R/W R/W R/W R/W R R/W R/W R
Initial
Bit
Bit Name Value R/W Description
7
MSTP47 1
R/W Module Stop 47
When the MSTP47 bit is set to 1, the supply of the
clock to the SCIF0 is halted.
0: SCIF0 runs.
1: Clock supply to SCIF0 halted.
6
MSTP46 1
R/W Module Stop 46
When the MSTP46 bit is set to 1, the supply of the
clock to the SCIF1 is halted.
0: SCIF1 runs.
1: Clock supply to SCIF1 halted.
5
MSTP45 1
R/W Module Stop 45
When the MSTP45 bit is set to 1, the supply of the
clock to the SCIF2 is halted.
0: SCIF2 runs.
1: Clock supply to SCIF2 halted.
4
MSTP44 1
R/W Module Stop 44
When the MSTP44 bit is set to 1, the supply of the
clock to the SCIF3 is halted.
0: SCIF3 runs.
1: Clock supply to SCIF3 halted.
3
⎯
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 May. 08, 2008 Page 999 of 1200
REJ09B0344-0200