SH7211 Datasheet, PDF (404/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 10.21 TIORL_0 (Channel 0)
Description
Bit 3 Bit 2 Bit 1 Bit 0 TGRC_0
IOC3 IOC2 IOC1 IOC0 Function
TIOC0C Pin Function
0
0
0
0
Output
Output retained*¹
1
compare
register*²
Initial output is 0
0 output at compare match
1
0
Initial output is 0
1 output at compare match
1
Initial output is 0
Toggle output at compare match
1
0
0
Output retained
1
Initial output is 1
0 output at compare match
1
0
Initial output is 1
1 output at compare match
1
Initial output is 1
Toggle output at compare match
1
0
0
0
Input capture Input capture at rising edge
1
register*²
Input capture at falling edge
1
X
Input capture at both edges
1
X
X
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down
[Legend]
X:
Don't care
Notes: 1. After power-on reset, 0 is output until TIOR is set.
2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 2.00 May. 08, 2008 Page 380 of 1200
REJ09B0344-0200