SH7211 Datasheet, PDF (1179/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
Page
10.4.8 Complementary 513
PWM Mode
(3) Interrupt Skipping in
Complementary PWM
Mode
(c) Buffer Transfer
Control Linked with
Interrupt Skipping
Figure 10.77 Example 515
of Operation when Buffer
Transfer is Linked with
Interrupt Skipping (BTE1
= 1 and BTE0 = 0)
Figure 10.78
516
Relationship between
Bits T3AEN and T4VEN
in TITCR and Buffer
Transfer-Enabled Period
10.4.11 External Pulse 528
Width Measurement
Figure 10.88 Example
of External Pulse Width
Measurement
(Measuring High Pulse
Width)
10.7.22 Simultaneous 565
Capture of TCNT_1 and
TCNT_2 in Cascade
Connection
12.6.1 Pin Status When 635
the WDT Issues a
Power-On Reset
Revision (See Manual for Details)
Description amended
… While this setting is valid, data is not transferred from the
buffer register outside the buffer transfer-enabled period.
There are two types of timing in which data is transferred from
the buffer register to the temporary register or to general
register, depending on the buffer register modification timing
after an interrupt occurrence.
Note that the buffer transfer-enabled period depends on the
T3AEN and T4VEN bit settings in the timer interrupt skipping
set register (TITCR).
Figure replaced
Figure replaced
Figure replaced
Description added
… In this case, the values of TCNT_1 = H'FFF1 and TCNT_2
= H'0000 should be transferred to TGRA_1 and TGRA_2 or to
TGRB_1 and TGRB_2, but the values of TCNT_1 = H'FFF0
and TCNT_2 = H'0000 are erroneously transferred.
The MTU2 additionally supports the function that can capture
TCNT_1 and TCNT_2 simultaneously via a single input
capture input. This function allows 32-bit counter fetches
without TCNT_1 and TCNT_2 capture timing deviation. For
details, see section 10.3.8, Timer Input Capture Control
Register (TICCR).
Description replaced
Rev. 2.00 May. 08, 2008 Page 1155 of 1200
REJ09B0344-0200