SH7211 Datasheet, PDF (641/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 12 Port Output Enable 2 (POE2)
12.3.2 Output Level Control/Status Register 1 (OCSR1)
OCSR1 is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
OSF1 -
-
-
-
- OCE1 OIE1 -
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/(W)*¹ R
R
R
R
R R/W*² R/W R
R
R
R
R
R
R
R
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
Initial
Bit
Bit Name Value
15
OSF1 0
14 to 10 ⎯
All 0
9
OCE1 0
8
OIE1
0
R/W Description
R/(W)*¹ Output Short Flag 1
Indicates that any one of the three pairs of MTU2 2-
phase outputs to be compared has simultaneously
become an active level.
[Clearing condition]
• By writing 0 to OSF1 after reading OSF1 = 1
[Setting condition]
• When any one of the three pairs of 2-phase outputs
has simultaneously become an active level
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W*² Output Short High-Impedance Enable 1
Specifies whether to place the pins in high-impedance
state when the OSF1 bit in OCSR1 is set to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
R/W Output Short Interrupt Enable 1
Enables or disables interrupt requests when the OSF1 bit
in OCSR is set to 1.
0: Interrupt requests disabled
1: Interrupt requests enabled
Rev. 2.00 May. 08, 2008 Page 617 of 1200
REJ09B0344-0200