SH7211 Datasheet, PDF (711/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.8 Bit Rate Register (SCBRR)
SCBRR is an 8-bit register that, together with the baud rate generator clock source selected by the
CKS[1:0] bits in the serial mode register (SCSMR), determines the serial transmit/receive bit rate.
The CPU can always read and write to SCBRR. SCBRR is initialized to H'FF by a power-on reset.
Each channel has independent baud rate generator control, so different values can be set in four
channels.
Bit: 7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The SCBRR setting is calculated as follows:
• Asynchronous mode:
(1) In normal mode (when the ABCS bit in SCSEMR is 0)
N=
Pφ
× 10⁶ − 1
64 × 2^2n-1 × B
(2) In serial extended mode (when the ABCS bit in SCSEMR is 1)
N=
Pφ
× 10⁶ − 1
32 × 2^2n-1 × B
• Clocked synchronous mode:
N=
Pφ
× 10⁶ − 1
8 × 2^2n-1 × B
B: Bit rate (bits/s)
N: SCBRR setting for baud rate generator (0 ≤ N ≤ 255)
(The setting must satisfy the electrical characteristics.)
Pφ: Operating frequency for peripheral modules (MHz)
n: Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n,
see table 15.3.)
Rev. 2.00 May. 08, 2008 Page 687 of 1200
REJ09B0344-0200