SH7211 Datasheet, PDF (559/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
(1) Input Capture/Compare Match Interrupt
An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1
by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt
request is cleared by clearing the TGF flag to 0. The MTU2 has 21 input capture/compare match
interrupts, six for channel 0, four each for channels 3 and 4, two each for channels 1 and 2, and
three for channel 5. The TGFE_0 and TGFF_0 flags in channel 0 are not set by the occurrence of
an input capture.
(2) Overflow Interrupt
An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to
1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing
the TCFV flag to 0. The MTU2 has five overflow interrupts, one for each channel.
(3) Underflow Interrupt
An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to
1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing
the TCFU flag to 0. The MTU2 has two underflow interrupts, one each for channels 1 and 2.
10.5.2 DMAC Activation
The DMAC can be activated by the TGRA input capture/compare match interrupt in each channel.
For details, see section 9, Direct Memory Access Controller (DMAC).
In the MTU2, a total of five TGRA input capture/compare match interrupts can be used as DMAC
activation sources, one each for channels 0 to 4.
Rev. 2.00 May. 08, 2008 Page 535 of 1200
REJ09B0344-0200