SH7211 Datasheet, PDF (335/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 9 Direct Memory Access Controller (DMAC)
Bit
Bit Name
28
RLD
27 to 24 ⎯
23
DO
22
TL
21, 20 ⎯
Initial
Value
0
All 0
0
0
All 0
R/W Descriptions
R/W Reload Function Enable or Disable
Enables or disables the reload function.
0: Disables the reload function
1: Enables the reload function
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid only in CHCR_0 to
CHCR_3. This bit is reserved in CHCR_4 and
CHCR_7; it is always read as 0 and the write value
should always be 0.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
R/W Transfer End Level
Specifies the TEND signal output is high active or low
active. This bit is valid only in CHCR_0 and CHCR_1.
This bit is reserved in CHCR_2 to CHCR_7; it is
always read as 0 and the write value should always be
0.
0: Low-active output from TEND
1: High-active output from TEND
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 May. 08, 2008 Page 311 of 1200
REJ09B0344-0200