SH7211 Datasheet, PDF (810/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 17 A/D Converter (ADC)
Table 17.6 A/D Conversion Time
Number of Required States
Item
Symbol Min.
Typ.
Max.
A/D conversion start delay time
t_D
11*¹
⎯
15*²
Analog input sampling time of dedicated t
⎯
30
⎯
SPLSH
sample-and-hold circuit for GrA and GrB
Offset canceling processing time
t_OFC
⎯
50
⎯
Analog input sampling time of sample- t_SPL
⎯
20
⎯
and-hold circuit common to all channels
A/D conversion complete processing
t_end
A/D conversion time
t_CONV
⎯
4
50n + 95*³ ⎯
Notes: 1. A/D converter activation by the MTU2 or MTU2S trigger signal.
2. A/D converter activation by an external trigger signal.
3. n: number of A/D conversion channels (n = 1 to 8)
⎯
50n + 99*³
TRGAN
(MTU2, MTU2S trigger signal)
ADST
tD
Sampling and
hold time (tSPLSH)
A/D conversion time (tCONV)
tOFC
Sampling and
hold time (tSPL)
Conversion complete
processing (tend)
A/D
converter
ADDR
ADF
Waiting
Sample-
and-hold
OFC
Sample-
and-hold
A/D conversion
Waiting
Conversion time
per channel
50 states
Aφ = 40 MHz: 1.25 μs
Figure 17.4 A/D Conversion Timing (Single-Cycle Scan Mode)
End of A/D
conversion
Rev. 2.00 May. 08, 2008 Page 786 of 1200
REJ09B0344-0200