SH7211 Datasheet, PDF (107/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 5 Exception Handling
5.2 Resets
5.2.1 Types of Reset
A reset is the highest-priority exception handling source. There are two kinds of reset, power-on
and manual. As shown in table 5.5, the CPU state is initialized in both a power-on reset and a
manual reset. On-chip peripheral module registers are initialized by a power-on reset, but not by a
manual reset.
Table 5.5 Exception Source Detection and Exception Handling Start Timing
Conditions for Transition to Reset State
Internal States
Type
RES or
MRES
WDT
H-UDI Command Overflow
CPU
On-Chip
Peripheral
WRCSR of WDT,
Modules, I/O Port FRQCR of CPG
Power-on Low
reset
High
—
—
H-UDI reset assert —
command is set
Initialized Initialized
Initialized Initialized
Initialized
Initialized
High
Command other
than H-UDI reset
assert is set
Power-on
reset
Initialized Initialized
Not initialized
Manual Low
—
reset
High
—
—
Manual
reset
Initialized Not initialized*
Initialized Not initialized*
Not initialized
Not initialized
Note: * The BN bit in IBNR of the INTC is initialized.
Rev. 2.00 May. 08, 2008 Page 83 of 1200
REJ09B0344-0200