SH7211 Datasheet, PDF (13/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

8.3.1 Address Map ......................................................................................................... 179
8.3.2 Setting Operating Modes ...................................................................................... 180
8.4 Register Descriptions ......................................................................................................... 182
8.4.1 Common Control Register (CMNCR) .................................................................. 183
8.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 7) ..................................... 186
8.4.3 CSn Space Wait Control Register (CSnWCR) (n = 0 to 7) .................................. 191
8.4.4 SDRAM Control Register (SDCR)....................................................................... 221
8.4.5 Refresh Timer Control/Status Register (RTCSR) ................................................. 225
8.4.6 Refresh Timer Counter (RTCNT)......................................................................... 227
8.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 228
8.5 Operation ........................................................................................................................... 229
8.5.1 Endian/Access Size and Data Alignment.............................................................. 229
8.5.2 Normal Space Interface......................................................................................... 232
8.5.3 Access Wait Control ............................................................................................. 236
8.5.4 CSn Assert Period Expansion ............................................................................... 238
8.5.5 MPX-I/O Interface................................................................................................ 239
8.5.6 SDRAM Interface ................................................................................................. 243
8.5.7 Burst ROM (Clock Asynchronous) Interface ....................................................... 278
8.5.8 SRAM Interface with Byte Selection.................................................................... 280
8.5.9 Burst ROM (Clock Synchronous) Interface.......................................................... 285
8.5.10 Wait between Access Cycles ................................................................................ 286
8.5.11 Bus Arbitration ..................................................................................................... 293
8.5.12 Others.................................................................................................................... 295
8.6 Usage Notes ....................................................................................................................... 298
8.6.1 Burst ROM Interface............................................................................................. 298
Section 9 Direct Memory Access Controller (DMAC) .......................................299
9.1 Features.............................................................................................................................. 299
9.2 Input/Output Pins ............................................................................................................... 302
9.3 Register Descriptions ......................................................................................................... 303
9.3.1 DMA Source Address Registers (SAR) ................................................................ 307
9.3.2 DMA Destination Address Registers (DAR) ........................................................ 308
9.3.3 DMA Transfer Count Registers (DMATCR) ....................................................... 309
9.3.4 DMA Channel Control Registers (CHCR) ........................................................... 310
9.3.5 DMA Reload Source Address Registers (RSAR) ................................................. 318
9.3.6 DMA Reload Destination Address Registers (RDAR) ......................................... 319
9.3.7 DMA Reload Transfer Count Registers (RDMATCR)......................................... 320
9.3.8 DMA Operation Register (DMAOR) ................................................................... 321
9.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3) .................. 325
9.4 Operation ........................................................................................................................... 327
Rev. 2.00 May. 08, 2008 Page xiii of xxiv
REJ09B0344-0200