SH7211 Datasheet, PDF (155/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 6 Interrupt Controller (INTC)
Interrupt acceptance
3 Icyc + m1 + m2
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc
m1 m2 m3
IRQ
Instruction (instruction replacing
interrupt exception handling)
F D E EMMM
First instruction in interrupt exception
service routine
FDE
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
F: Instruction fetch. Instruction is fetched from memory in which program is stored.
D: Instruction decoding. Fetched instruction is decoded.
E: Instruction execution. Data operation or address calculation is performed in accordance with the result of decoding.
M: Memory access. Memory data access is performed.
Figure 6.4 Example of Pipeline Operation when IRQ Interrupt is Accepted
(No Register Banking)
Rev. 2.00 May. 08, 2008 Page 131 of 1200
REJ09B0344-0200