SH7211 Datasheet, PDF (116/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 5 Exception Handling
5.5.3 Interrupt Exception Handling
When an interrupt occurs, its priority level is ascertained by the interrupt controller (INTC). NMI
is always accepted, but other interrupts are only accepted if they have a priority level higher than
the priority level set in the interrupt mask level bits (I3 to I0) of the status register (SR).
When an interrupt is accepted, interrupt exception handling begins. In interrupt exception
handling, the CPU fetches the exception service routine start address which corresponds to the
accepted interrupt from the exception handling vector table, and saves SR and the program counter
(PC) to the stack. In the case of interrupt exception handling other than NMI or UBC with usage
of the register banks enabled, general registers R0 to R14, control register GBR, system registers
MACH, MACL, and PR, and the vector number of the interrupt exception handling to be executed
are saved in the register banks. In the case of exception handling due to an address error, NMI
interrupt, UBC interrupt, or instruction, saving is not performed to the register banks. If saving has
been performed to all register banks (0 to 14), automatic saving to the stack is performed instead
of register bank saving. In this case, an interrupt controller setting must have been made so that
register bank overflow exceptions are not accepted (the BOVE bit in IBNR of the INTC is 0). If a
setting to accept register bank overflow exceptions has been made (the BOVE bit in IBNR of the
INTC is 1), register bank overflow exception occurs. Next, the priority level value of the accepted
interrupt is written to the I3 to I0 bits in SR. For NMI, however, the priority level is 16, but the
value set in the I3 to I0 bits is H'F (level 15). Then, after jumping to the start address fetched from
the exception handling vector table, program execution starts. The jump that occurs is not a
delayed branch. See section 6.6, Operation, for further details of interrupt exception handling.
Rev. 2.00 May. 08, 2008 Page 92 of 1200
REJ09B0344-0200