SH7211 Datasheet, PDF (12/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

6.8.3 Save and Restore Operations after Saving to All Banks....................................... 138
6.8.4 Register Bank Exception ...................................................................................... 139
6.8.5 Register Bank Error Exception Handling ............................................................. 139
6.9 Data Transfer with Interrupt Request Signals .................................................................... 140
6.9.1 Handling Interrupt Request Signals as Sources
for CPU Interrupt but Not DMAC Activating ...................................................... 141
6.9.2 Handling Interrupt Request Signals as Sources
for Activating DMAC but Not CPU Interrupt ...................................................... 141
6.10 Usage Note......................................................................................................................... 141
6.10.1 Timing to Clear an Interrupt Source ..................................................................... 141
Section 7 User Break Controller (UBC).............................................................. 143
7.1 Features.............................................................................................................................. 143
7.2 Input/Output Pin ................................................................................................................ 145
7.3 Register Descriptions ......................................................................................................... 145
7.3.1 Break Address Register_0 (BAR_0)..................................................................... 146
7.3.2 Break Address Mask Register_0 (BAMR_0) ....................................................... 147
7.3.3 Break Bus Cycle Register_0 (BBR_0).................................................................. 148
7.3.4 Break Address Register_1 (BAR_1)..................................................................... 150
7.3.5 Break Address Mask Register_1 (BAMR_1) ....................................................... 151
7.3.6 Break Bus Cycle Register_1 (BBR_1).................................................................. 152
7.3.7 Break Address Register_2 (BAR_2)..................................................................... 154
7.3.8 Break Address Mask Register_2 (BAMR_2) ....................................................... 155
7.3.9 Break Bus Cycle Register_2 (BBR_2).................................................................. 156
7.3.10 Break Address Register_3 (BAR_3)..................................................................... 158
7.3.11 Break Address Mask Register_3 (BAMR_3) ....................................................... 159
7.3.12 Break Bus Cycle Register_3 (BBR_3).................................................................. 160
7.3.13 Break Control Register (BRCR) ........................................................................... 162
7.4 Operation ........................................................................................................................... 166
7.4.1 Flow of the User Break Operation ........................................................................ 166
7.4.2 Break on Instruction Fetch Cycle ......................................................................... 167
7.4.3 Break on Data Access Cycle................................................................................. 168
7.4.4 Value of Saved Program Counter ......................................................................... 169
7.4.5 Usage Examples.................................................................................................... 170
7.5 Usage Notes ....................................................................................................................... 173
Section 8 Bus State Controller (BSC) .................................................................175
8.1 Features.............................................................................................................................. 175
8.2 Input/Output Pins............................................................................................................... 178
8.3 Area Overview................................................................................................................... 179
Rev. 2.00 May. 08, 2008 Page xii of xxiv
REJ09B0344-0200