SH7211 Datasheet, PDF (793/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Section 17 A/D Converter (ADC)
Section 17 A/D Converter (ADC)
This LSI includes a successive approximation type 12-bit A/D converter.
17.1 Features
• 12-bit resolution
• Input channels
Eight channels (two independent A/D conversion modules)
• High-speed conversion
When Aφ = 40 MHz: Minimum 1.25 μs per channel
AD clock = 40 MHz, 50 conversion states
• Two operating modes
⎯ Single-cycle scan mode: Continuous A/D conversion on one to eight channels
⎯ Continuous scan mode: Repetitive A/D conversion on one to eight channels
• A/D data registers
Eight A/D data registers (ADDR) are provided. A/D conversion results are stored in A/D data
registers (ADDR) that correspond to the input channels.
• Sample-and-hold function
A sample-and-hold circuit is built into the A/D converter of this LSI, simplifying the
configuration of the external analog input circuitry. Multiple channels can be sampled
simultaneously because sample-and-hold circuits can be dedicated for channels 0 to 2 and 8 to
10.
⎯ Group A (GrA): Analog input pins selected from channels 0, 1, and 2 can be
simultaneously sampled.
• Three methods for starting conversion
Software: Setting of the ADST bit in ADCR
Timer: TRGAN, TRG0N, TRG4AN, and TRG4BN from the MTU2
TRGAN, TRG4AN, and TRG4BN from the MTU2S
External trigger: ADTRG (LSI pin)
• Selectable analog input channel
A/D conversion of a selected channel is accomplished by setting the A/D analog input channel
select registers (ADANSR).
• A/D conversion end interrupt and DMAC transfer function is supported
On completion of A/D conversion, A/D conversion end interrupts (ADI) can be generated and
the DMAC can be activated by ADI.
Rev. 2.00 May. 08, 2008 Page 769 of 1200
REJ09B0344-0200