SH7211 Datasheet, PDF (1191/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Item
Page
21.5.2 User Program 934
Mode
(4) Erasing and
Programming Procedure
in User Program Mode
Figure 21.13 Sample
Procedure of Repeating
RAM Emulation, Erasing,
and Programming
(Overview)
935
21.7.2 Interrupts during 945
Programming/Erasing
Figure 21.18 Timing of
Contention between
SCO Download Request
and Interrupt Request
Revision (See Manual for Details)
Figure amended
1
Start procedure program
Set FTDAR to H'00
(Specify H'FFF81000 as
download destination)
Download erasing program
Initialize erasing program
Set FTDAR to H'02
(Specify H'FFF82000 as
download destination)
Erase relevant block
(execute erasing program)
Set FMPDR to H'FFF86000 to
program relevant block
(execute programming program)
Confirm operation
Download programming
program
Initialize programming
program
1
End?
No
Yes
End procedure program
Description amended
2. Be sure to initialize both the erasing program and
programming program.
Initialization by setting the FPEFEQ and FUBRA
parameters must be performed for both the erasing
program and the programming program. Initialization must
be executed for both entry addresses: (download start
address for erasing program) + 32 bytes (H'FFF81020 in
this example) and (download start address for
programming program) + 32 bytes (H'FFF82020 in this
example).
Figure amended
CPU cycle
CPU operation for instruction
that sets SCO bit to 1
n
Fetch
n+1
Decoding
n+2
Execution
n+3
Execution
n+4
Execution
Interrupt acceptance
(a)
(b)
(a) When the interrupt is accepted at the (n + 1) cycle or before
After the interrupt processing completes, the SCO bit is set to 1 and download is executed.
(b) When the interrupt is accepted at the (n + 2) cycle or later
The interrupt will conflicts with the SCO download request. Ensure that no interrupt is generated.
Rev. 2.00 May. 08, 2008 Page 1167 of 1200
REJ09B0344-0200