SH7211 Datasheet, PDF (201/1228 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family

Figure 8.1 shows a block diagram of the BSC.
Section 8 Bus State Controller (BSC)
BREQ
BACK
WAIT
Bus
mastership
controller
Wait
controller
CMNCR
CS0WCR
CS7WCR
CS0 to CS7
MD1, MD0
Area
controller
CS0BCR
CS7BCR
A25 to A0,
D15 to D0
BS, RD/WR,
RD, WE1, WE0,
RASL,
CASL
CKE, DQMxx, AH,
REFOUT
Memory
controller
Refresh
controller
SDCR
RTCSR
RTCNT
Comparator
RTCOR
[Legend]
CMNCR: Common control register
CSnWCR: CSn space wait control register (n = 0 to 7)
CSnBCR: CSn space bus control register (n = 0 to 7)
SDCR: SDRAM control register
RTCSR: Refresh timer control/status register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
BSC
Figure 8.1 Block Diagram of BSC
Rev. 2.00 May. 08, 2008 Page 177 of 1200
REJ09B0344-0200